In recent years, as for liquid crystal display devices, a gate driver (a scanning signal line drive circuit) for driving gate bus lines (scanning signal lines) have been increasingly monolithic. Heretofore, a gate driver has been often mounted as an IC (Integrated Circuit) chip around a substrate that forms a liquid crystal panel. On the other hand, recently, a structure that a gate driver is directly formed on a substrate has been gradually and increasingly adopted. Such a gate driver is called a “monolithic gate driver” or the like. In a liquid crystal display device including the monolithic gate driver, typically, a thin-film transistor made of amorphous silicon (a-Si) has been adopted as a driving element. However, recently, a thin-film transistor made of polycrystalline silicon, microcrystalline silicon, an oxide semiconductor (e.g., IGZO) or the like tends to be adopted as the driving element.
By the way, a display part of an active matrix-type liquid crystal display device includes a pixel circuit including a plurality of source bus lines (video signal lines), a plurality of gate bus lines, and a plurality of pixel formation portions formed in correspondence with intersections between the plurality of source bus lines and the plurality of gate bus lines respectively. The plurality of pixel formation portions are arranged in a matrix to form a pixel array. Each of the pixel formation portions includes a thin-film transistor which is a switching element having a gate terminal connected to the gate bus line passing through the corresponding intersection and a source terminal connected to the source bus line passing through this intersection, a pixel capacitance for holding a pixel voltage value, and the like. Moreover, the active matrix-type liquid crystal display device includes such a gate driver as described above, and a source driver (a video signal line drive circuit) for driving the source bus line.
A video signal indicating the pixel voltage value is transmitted by the source bus line. However, the respective source bus lines are incapable of concurrently (simultaneously) transmitting the video signals indicating the pixel voltage values on the plural rows. Therefore, the writing of the video signals into (electrical charging to) the pixel capacitances of the pixel formation portions arranged in the matrix is sequentially performed on a row-by-row basis. Hence, the gate driver is configured with a shift register including a plurality of stages in order that the plurality of gate bus lines are sequentially selected every predetermined period. Then, active scanning signals are sequentially output from the respective stages of the shift register (hereinafter, a circuit that constitutes each stage of the shift register will also be referred to as a “stage constituent circuit”), so that the video signals are sequentially written into the pixel capacitances on the row-by-row basis, as described above.
In a conventional display device, each stage (each stage constituent circuit) of a shift register is configured as shown in FIG. 36 (FIG. 2 in Japanese Patent Application Laid-Open No. 2006-127630), for example. As shown in FIG. 36, the stage constituent circuit includes an output control transistor having a source terminal connected to an output terminal for a scanning signal, and a drain terminal to which a clock signal is fed. Then, an ON/OFF state of the output control transistor is controlled in such a manner that a potential of a node connected to a gate terminal of the output control transistor is controlled, and a potential of the clock signal at the time when the output control transistor is in the ON state appears as a scanning signal. Herein, according to the configuration shown in FIG. 36, a gate voltage of the output control transistor (a voltage of the node A) is raised step by step using the scanning signal to be output from the stage prior to the two stages and the scanning signal to be output from the preceding stage. Thus, the gate voltage of the output control transistor is remarkably raised, and the rising and falling of the scanning signal is rapidly performed. Note that, in the following, a period in which the scanning signal fully rises and the inherent writing (of video signal) into the pixel capacitance is performed is referred to as a “full charge period”. Moreover, a period from a point in time at which the scanning signal starts to rise to a point in time at which the scanning signal starts to fall (a period in which an operation for the writing into the pixel capacitance is performed) is referred to as a “writing operation period”.
In addition to Japanese Patent Application Laid-Open No. 2006-127630 described above, Published Japanese Translation of PCT Application No. 2008-508654, Published Japanese Translation of PCT Application No. 2008-537275, Japanese Patent Application Laid-Open No. 2003-202840 and Japanese Patent Application Laid-Open No. 2008-61323 each disclose a configuration of a shift register provided in a display device or the like.